Toward a logical qubit demonstration with trapped ions in a scalable quantum computing architecture

Realisation of a `beneficial' quantum error correcting code in a scalable architecture is an important milestone for quantum computing. This task is made difficult by the juxtaposed requirements of high-fidelity quantum logic, benefitting from well isolated qubits, and many-qubit entanglement benefitting from a high degree of qubit connectivity. This thesis seeks to address these competing needs within a computing architecture based on a 2D array of linear ion traps connected via junctions, following three distinct research avenues: Designing, simulating and experimentally implementing ion transport protocols for the non-trivial potential landscape in the vicinity of junctions in Paul traps, utilising finite element simulations of the electric potential produced by a given trap geometry. Analysing sources of decoherence in microfabricated ion traps, characterising error mitigation strategies both experimentally and numerically and proposing design principles for coherent voltage noise cancellation within specialised entangling gate zones. Co-design through computational studies of the performance of quantum error correction with the 17 qubit Surface Code under a variety of experimentally motivated noise models representative of different architectural choices.